1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating an integrated circuit with high density, such as a non-volatile multi-mask read only memory (ROM).
2. Field of the Related Art
Being restricted by the technical limit of designing a memory, to reduce the dimension of a memory device, the technique of process needs to be improved. The conventional ROM is assembled by an array of field effect transistor metal oxide semiconductors (FET MOS). Each memory cell comprises a single field effect device disposed at the intersection of a parallel conductive line buried in the substrate and a vertical conductive line formed on the substrate. The formation of each field effect transistor provides the choice between either of two predetermined values depending on the characteristics of transistor, such as the threshold voltage. By doping the channel region of a transistor, a higher threshold voltage is obtained. The transistor is not turned on by applying the voltage Vcc to the gate. On the contrary, with the undoped channel region, the transistor is turned on by the voltage Vcc applied to the gate. Binary data are stored into the memory cell by selectively doping the channel regions. That is, a logic "0" is stored in a transistor with a doped channel region, and a logic "1" lis stored in a transistor with an undoped channel region.
FIG. 1 is a top view of a region (including four memory cells) of a conventional mask ROM. Referring to FIG. 1, a mask ROM is formed on a substrate 10 having a P-type surface. The mask ROM comprises an array of parallel buried bit lines 12, 14 and 16 which are N-type bit lines formed by selectively doping the substrate 10, and an array of parallel word lines 18 and 20 expanding on the substrate 10. The array of word lines 18 and 20 is perpendicular to the array of bit lines 12, 14, and 16. In addition, a silicon oxide layer is formed between two word lines 18 and 20 for the purpose of isolation. Normally, in a mask ROM, a structure of sharing a word line is adapted. The bit lines 12, 14, and 16 are the source/drain regions of field effect transistors, whereas, the regions 22, 24, 26, and 28 connecting with the bit lines 12, 14, and 16 under the word lines 18 and 20 are the channel regions of field effects transistors.
FIG. 2 is a cross sectional view of a conventional ROM shown as 2-2' in FIG. 1. Referring to FIG. 2, to form a buried bit line, a proper mask (not shown on the figure) is used to cover the substrate 10. An N-type dopant is implanted into the substrate 10 to form bit lines 12, 14, and 16. The doped substrate 10 is then put into an environment of oxygen to activate the dopant within the bit lines 12, 14, and 16, and to form an oxide layer. The oxide layer comprises a thinner gate oxide layer 30 on the channel region 22 and 24, and a thicker oxide layer 32 covering the bit lines 12, 14, and 16. The thicker oxide layer 32 is formed because of the much larger oxidation diffusion rate of the heavily doped N-type dopant in the bit lines 12, 14 and 16 than the lightly doped P-type ions in the channel regions 22 and 24. After the formation of the thicker oxide layer 32, a doped poly-silicon layer is formed on the gate oxide layer 30 and the thicker oxide layer 32. The poly-silicon layer is then defined to form a gate electrode 18 of the field effect transistor. The gate electrode is used as a word line in the ROM.
As the size of the memory becomes smaller and smaller, the width of the buried bit lines becomes narrower and narrower. The space of the bit line also shrinks further. The smaller the bit line is, the larger the resistance is obtained. Thus, the speed to access the data in a ROM is slower. The dimension of a transistor is limited in the consideration of access speed. On the other hand, the conventional multi-state method of fabricating a ROM is very complex. Moreover, it is difficult to control the dosage for the formation of different threshold voltage, and therefore, it is difficult to obtain a larger data storage.